Integrated circuit memory device having delayed write capability
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United States of America Patent
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Apr 15, 2008
Grant Date -
Jun 28, 2007
app pub date -
Mar 2, 2007
filing date -
Oct 10, 1997
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
An integrated circuit memory device has a first set of pins to receive, using a clock signal, a row address followed by a column address. The device has a second set of pins to receive, using the clock signal, a sense command and a write command. The sense command specifies that the device activate a row of memory cells identified by the row address. The write command specifies that the memory device receive write data and store the write data at a location, identified by the column address, in the row of memory cells. The write command is posted internally to the memory device after a first delay has transpired from a first time period in which the write command is received at the second set of pins. The write data is received at a third set of pins after a second delay has transpired from the first time period.
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