Method and apparatus for selecting an instruction thread for processing in a multi-thread processor
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United States of America Patent
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Apr 15, 2008
Grant Date -
Oct 28, 2004
app pub date -
Apr 25, 2003
filing date -
Apr 25, 2003
priority date (Note) -
Expired
status (Latency Note)
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Abstract
The selection between instruction threads in a SMT processor for the purpose of interleaving instructions from the different instruction threads may be modified to accommodate certain processor events or conditions. During each processor clock cycle, an interleave rule enforcement component produces at least one base instruction thread selection signal that indicates a particular one of the instruction threads for passing an instruction from that particular thread into a stream of interleaved instructions. Thread selection modification is provided by an interleave modification component that generates a final thread selection signal based upon the base thread selection signal and a feedback signal derived from one or more conditions or events in the various processor elements. This final thread selection signal may indicate the same instruction thread indicated by the base thread selection signal or a different one of the instruction threads for passing an instruction into the interleaved stream of instructions.
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