Circuit and method for latch bypass
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United States of America Patent
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Apr 22, 2008
Grant Date -
Sep 27, 2007
app pub date -
Mar 24, 2006
filing date -
Mar 24, 2006
priority date (Note) -
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status (Latency Note)
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Abstract
A device includes a first combinatorial logic stage having a first input to receive a first data value, a second input to receive a bypass value and an output to provide one of a representation of the first data value or a first predetermined value based on the bypass value. The device further includes a latch stage having a first input to receive a second data value, a second input to receive the bypass value and an output to provide one of a latched representation of the second data value or a second predetermined value based on the bypass value. The device additionally includes a second combinatorial logic stage having a first input coupled to the output of the first combinatorial logic stage, a second input coupled to the output of the latch stage, and an output.
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