Flash memory device capable of preventing an overerase of flash memory cells and erase method thereof
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United States of America Patent
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Apr 29, 2008
Grant Date -
Aug 9, 2007
app pub date -
Feb 1, 2007
filing date -
Jul 28, 1999
priority date (Note) -
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Abstract
We describe a NAND flash memory device including a memory cell array formed on a substrate including a plurality of cell strings each including a string selecting transistor, a ground selecting transistor, and plural memory cells serially coupled between the string selecting transistor and the ground selecting transistor. A high voltage generator is configured to supply a bulk voltage to the substrate and an erase control circuit is configured to stepwise increase the bulk voltage during a first period of an erase operation and to maintain the bulk voltage substantially constant during a second period of the erase operation.
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