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Abstract

A pattern-dependent model is used to predict characteristics of an integrated circuit that is to be fabricated in accordance with a design by a process. The process includes (a) a fabrication process that will impart topographical variation to the integrated circuit and (b) a lithography or etch process, the lithography or etch process using a mask produced from the design. The lithography or etch process and the fabrication process interact to cause the predicted characteristics to differ from the design. The mask is adjusted in response to characteristics predicted by the model, to reduce the effect of the interacting of the lithography or etch process and the fabrication process. A location on an integrated circuit is predicted for which a lithography tool would not produce a satisfactory feature dimension without a degree of adjustment of the tool during fabrication to accommodate a focus limitation of the tool, and the design of at least one mask derived from the design is adjusted to enable the lithography tool to produce a satisfactory feature dimension at the locations. A virtual adjustment is effected of a distance of a lithographic tool from a location in a region of a wafer, the virtual adjustment being effected by using a mask having a mask layout that has been generated based on a pattern-dependent model prediction that the location in the region of the wafer would not otherwise have a satisfactory feature dimension due to a focus limitation of the lithographic tool. A pattern-dependent model is used to predict topography variations that will occur in an integrated circuit as a result of processing up to a predetermined lithographic process step, and designs of masks used in the lithographic process step are adjusted to accommodate the topography variations.

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