Method, circuit and systems for erasing one or more non-volatile memory cells
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United States of America Patent
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May 6, 2008
Grant Date -
Jul 20, 2006
app pub date -
Jan 19, 2006
filing date -
Jan 19, 2005
priority date (Note) -
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Abstract
The present invention is a method, circuit and system for erasing one or more non-volatile memory ('NVM') cells in an NVM array or array segment. According to some embodiments of the present invention, one or more erase pulse parameters may be associated with each of a number of array segments within an NVM array. Separate erase pulse parameters may be associated with anywhere from one to all of the array segments within an NVM array. According to some embodiments of the present invention, a characteristic of an erase pulse (e.g. pulse amplitude, pulse duration, etc.) applied to one or more NVM cells within an array segment may be at least partially based on one or more erase pulse parameters associated with the given array segment.
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