Semiconductor integrated circuit and memory test method
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United States of America Patent
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May 13, 2008
Grant Date -
Sep 29, 2005
app pub date -
Jun 2, 2005
filing date -
Aug 30, 2002
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A semiconductor integrated circuit has a memory operating on a first clock. A memory device captures first output data, being output from the memory in synchronization with the first clock, depending on a second clock having a frequency equal to or less than the first clock. An expected value comparison section, operating on the second clock, compares second output data being output from the memory device and third output data being output from the memory immediately after the output of the first output data with a predetermined expected value.
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