Multi-layer printed wiring board including an alignment mark as an index for a position of via holes
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United States of America Patent
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May 20, 2008
Grant Date -
Jun 22, 2006
app pub date -
Jan 13, 2006
filing date -
Dec 11, 1997
priority date (Note) -
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status (Latency Note)
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Abstract
A multi-layer printed wiring board includes a board covered with a conductor layer, an interlayer insulating resin layer, an etched metal film on the interlayer insulating resin layer, and a via hole. The interlayer insulating resin layer has a fibrous substrate. The via hole has an electrolytic plated film and an electrolessly plated film and connects the conductor layer of the board and the etched metal film.
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