Methods for tiling integrated circuit designs
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United States of America Patent
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May 20, 2008
Grant Date -
Aug 23, 2007
app pub date -
Feb 17, 2006
filing date -
Feb 17, 2006
priority date (Note) -
Expired
status (Latency Note)
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Abstract
Methods for routing in the design of integrated circuits (ICs) to simplify the routing task. The method includes dividing a given IC design into a limited number of non-overlapping tiles, and then routing all tiles in parallel, each tile being independently routed by a standard router. Thereafter, routed tiles are assembled to form a routing solution for the entire IC. Details of exemplary methods are disclosed.
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