Integrated stress relief pattern and registration structure
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United States of America Patent
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May 27, 2008
Grant Date -
Aug 16, 2007
app pub date -
Apr 3, 2007
filing date -
Jun 1, 2004
priority date (Note) -
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Abstract
A semiconductor die having an integrated circuit region formed in a substrate comprises at least one die-corner-circuit-forbidden (DCCF) region disposed in the substrate, proximate to the integrated circuit region; and at least one registration feature formed within the at least one DCCF region. The at least one registration feature comprises a structure selected from the group consisting of a laser fuse mark, an alignment mark, and a monitor mark.
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