Method and apparatus for universal program controlled bus architecture
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United States of America Patent
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Jun 3, 2008
Grant Date -
Sep 14, 2006
app pub date -
Sep 1, 2005
filing date -
Sep 4, 1996
priority date (Note) -
Expired
status (Latency Note)
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Abstract
An integrated circuit including a programmable logic array with a plurality of logic cells and programmable interconnections to receive input signals and to perform logical functions to transmit output signals. The integrated circuit may also include megacells comprising a plurality of functional blocks receiving inputs and transmitting outputs. The integrated circuit may also include a programmable interconnections subsystem to cascade the megacells. The megacells are coupled to the programmable logic array.
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