Characterization and reduction of variation for integrated circuits

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United States of America Patent

PATENT NO 7383521
APP PUB NO 20050132306A1
SERIAL NO

11005651

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Abstract

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A method and system are described to reduce process variation as a result of the semiconductor processing of films in integrated circuit manufacturing processes. The described methods use process variation and electrical impact to modify the design and manufacture of integrated circuits.

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Patent Owner(s)

  • CADENCE DESIGN SYSTEMS, INC.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Mehrotra, Vikas Fremont, CA 17 2345
Smith, Taber H Fremont, CA 24 4049
White, David Cambridge, MA 205 6959

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