Methods of operating a bistable resistance random access memory with multiple memory layers and multilevel memory states
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United States of America Patent
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Jun 17, 2008
Grant Date -
Apr 24, 2008
app pub date -
Oct 24, 2006
filing date -
Oct 24, 2006
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Abstract
A method is described for operating a bistable resistance random access memory having two memory layer stacks that are aligned in series is disclosed. The bistable resistance random access memory comprises two memory layer stacks per memory cell, the bistable resistance random access memory operates in four logic states, a logic '00' state, a logic '01' state, a logic '10' state and a logic '11' state. The relationship between the four different logic states can be represented mathematically by the two variables n and f and a resistance R. The logic '0' state is represented by a mathematical expression (1+f)R. The logic '1' state is represented by a mathematical expression (n+f)R. The logic '2' state is represented by a mathematical expression (1+nf)R. The logic '3' state is represented by a mathematical expression n(1+f)R.
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