Method and apparatus for performing multiply-add operations on packed data
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United States of America Patent
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Jul 1, 2008
Grant Date -
Jun 17, 2004
app pub date -
Jun 30, 2003
filing date -
Aug 31, 1995
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data.
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