Memory device signaling system and method with independent timing calibration for parallel signal paths
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United States of America Patent
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Jul 8, 2008
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app pub date -
Jan 18, 2005
filing date -
Oct 22, 2001
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Abstract
A memory system includes a memory controller and a memory component coupled to each other. The memory controller includes an interface to receive a first signal and a second signal from the memory component, wherein the first signal comprises a first symbol and the second signal comprises a second symbol. A first circuit of the memory controller receives the first signal by sampling the first symbol using a first timing offset relative to a reference clock signal, and a second circuit of the memory controller receives the second signal by sampling the second symbol using a second timing offset relative to the reference clock signal. The first timing offset is independent of the second timing offset.
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