Net list producing device producing a net list with an interconnection parasitic element by hierarchical processing
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United States of America Patent
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Jul 8, 2008
Grant Date -
Aug 24, 2006
app pub date -
Feb 22, 2006
filing date -
Feb 24, 2005
priority date (Note) -
Expired
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Abstract
A memory cell information producing unit obtains physical terminal coordinates, physical terminal names and logical terminal names of a memory cell and layout data, and operates based on them to specify parasitic elements parasitic on interconnections of the memory cell, and to produce memory cell information including the physical terminal names and representing physical properties and a connection relationship of inner elements of the memory cell and the parasitic elements. Memory cell array information producing unit obtains connection information determining the connection relationship of physical terminals of the memory cell, assigns node names to the physical terminals of the memory cell based on the connection information, and produces memory cell array information representing the node names of all the memory cells. A memory cell array net list producing unit produces a net list of the memory cell array formed of the memory cell information and the memory cell array information.
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- 15 United States
- 10 France
- 8 Japan
- 7 China
- 5 Korea
- 2 Other
Patent Owner(s)
- RENESAS ELECTRONICS CORPORATION
International Classification(s)
Inventor(s)
Inventor Name | Address | # of filed Patents | Total Citations |
---|---|---|---|
Kanamoto, Toshiki | Tokyo, JP | 11 | 169 |
Shirota, Mitsutoshi | Tokyo, JP | 3 | 17 |
Uchimura, Michiko | Tokyo, JP | 2 | 3 |
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Fee | Large entity fee | small entity fee | micro entity fee |
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Surcharge after expiration - Late payment is unavoidable | $700.00 | $350.00 | $175.00 |
Surcharge after expiration - Late payment is unintentional | $1,640.00 | $820.00 | $410.00 |
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