A Galois field multiplier array includes a 1.sup.st register, a 2.sup.nd register, a 3.sup.rd register, and a plurality of multiplier cells. The 1.sup.st register stores bits of a 1.sup.st operand. The 2.sup.nd register stores bits of a 2.sup.nd operand. The 3.sup.rd register stores bits of a generating polynomial that corresponds to one of a plurality of applications (e.g., FEC, CRC, Reed Solomon, et cetera). The plurality of multiplier cells is arranged in rows and columns. Each of the multiplier cells outputs a sum and a product and each cell includes five inputs. The 1.sup.st input receives a preceding cell's multiply output, the 2.sup.nd input receives at least one bit of the 2.sup.nd operand, the 3.sup.rd input receives a preceding cell's sum output, a 4.sup.th input receives at least one bit of the generating polynomial, and the 5.sup.th input receives a feedback term from a preceding cell in a preceding row. The multiplier cells in the 1.sup.st row have the 1.sup.st input, 3.sup.rd input, and 5.sup.th input set to corresponding initialization values in accordance with the 2.sup.nd operand.
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