Importance

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Abstract

A non-volatile memory array including a plurality of memory units is provided. Each memory unit is serially connected with a select transistor and a memory cell. A source region is next to the select transistor while a drain region is next to the memory cell. The drain lines are arranged in parallel in column direction and connected with the drain regions of the memory units in one column. The bit lines are arranged in parallel in row direction and connected with the source regions of the memory units in one row. The word lines are arranged in parallel in column direction and connected with the select gates of the memory units in one column. The control lines are arranged in parallel in column direction and connected with the control gates of the memory units in one column. The control lines are grouped by two and electrically connected with each other.

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First Claim