System and method for optimized test and configuration throughput of electronic circuits
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United States of America Patent
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Jul 29, 2008
Grant Date -
Mar 17, 2005
app pub date -
Jul 22, 2004
filing date -
Jul 23, 2003
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A system and method for maximizing the throughput of test and configuration in the manufacture of electronic circuits and systems. The system employs a tester having a flexible parallel test architecture with expandable resources that can accommodate a selected number of units under test (UUTs). The parallel test architecture is configurable to accept separate banks or partitions of UUTs, thereby enabling the system to obtain an optimal or maximum achievable throughput of test and configuration for the UUTs. The system determines an optimal or maximum achievable throughput by calculating a desired number N of UUTs to be tested/configured in parallel. Testing or configuring this desired number of UUTs in parallel allows the handling time to be balanced with the test and configuration times, thereby resulting in the maximum achievable throughput.
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