Arithmetic processing apparatus
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United States of America Patent
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-
Aug 12, 2008
Grant Date -
Apr 21, 2005
app pub date -
Sep 8, 2004
filing date -
Sep 11, 2003
priority date (Note) -
Expired
status (Latency Note)
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Abstract
The arithmetic processing apparatus of the present invention is an arithmetic processing apparatus that can be reconfigured in accordance with a processing mode and has a plurality of arranged unit arithmetic circuits. Each unit arithmetic circuit includes at least one input terminal, at least one output terminal, a first register which holds data, an adder which calculates a sum of two pieces of data, a second register which holds data, a bit shifter which shifts data left or right, a subtractor which calculates a difference between two pieces of data, an absolute value calculating unit which calculates an absolute value of data, and a path setting unit which sets a path according to the processing mode connecting among these circuit elements.
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