Semiconductor integrated circuit and testing method therefor
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United States of America Patent
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Aug 19, 2008
Grant Date -
Aug 16, 2007
app pub date -
Feb 13, 2007
filing date -
Feb 16, 2006
priority date (Note) -
Expired
status (Latency Note)
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Abstract
The present invention provides a semiconductor integrated circuit that is provided with an address generation circuit that selectively generates an address of a memory cell substituted by a redundancy memory cell based on a defective memory cell address retained in an address retention circuit, and a control circuit that selectively tests the redundancy memory cell by performing a retest on whether the substitution is successful or not based on the address generated by the address generation circuit.
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