Data link/physical layer packet diversion and insertion
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United States of America Patent
Stats
-
Aug 19, 2008
Grant Date -
Oct 16, 2003
app pub date -
Jul 30, 2001
filing date -
Jul 30, 2001
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A buffering structure including a number of storage structures and associated diversion and/or insertion logic, is provided to facilitate one or more selected ones of post-switching, pre-medium placement, diversion and/or insertion of egress packets, and post-medium extraction, pre-switching, diversion and/or insertion of ingress packets, during data link/physical layer processing of networking traffic. In selected applications, the buffering structure is provided as an integral part of a single ASIC multi-protocol networking processor having data link/physical layer processing components for a number of datacom and telecom protocols. In one of the selected applications, the single ASIC multi-protocol networking processor is employed in conjunction with other optical and electro components to form an integral optical networking module in support of optical-electro networking for the datacom/telecom protocols.
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