Data processing without processor core intervention by chain of accelerators selectively coupled by programmable interconnect network and to memory
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United States of America Patent
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Aug 19, 2008
Grant Date -
Nov 30, 2006
app pub date -
May 24, 2005
filing date -
May 24, 2005
priority date (Note) -
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Abstract
A programmable digital signal processor includes a plurality of memory units, a plurality of accelerator units and a processor core. The digital signal processor also includes a programmable network that may be configured to selectively provide connectivity between the memory units, the accelerator units, and the processor core. Each of the accelerator units may be configured to perform one or more dedicated functions. The processor core may include an execution unit that may be configured to execute instructions that are associated with datapath flow control. The programmable network may be configured to selectively provide the connectivity in response to execution of particular instructions.
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