Semiconductor memory device having a test control circuit
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United States of America Patent
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Sep 2, 2008
Grant Date -
Nov 30, 2006
app pub date -
Dec 8, 2005
filing date -
May 30, 2005
priority date (Note) -
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Abstract
A semiconductor memory device having a test control circuit includes a cell array, a BIST (built-in self test) circuit adapted and configured to perform a BIST operation on the cell array, a BISR (built-in self repair) circuit adapted and configured to perform a BISR operation on the cell array, and a command decoder adapted and configured to generate a first control signal for selecting a BIST operation by the BIST circuit or a test by an external tester and a second control signal for controlling a BISR operation by the BISR circuit. As a result, a test by an external tester, a BIST (built-in self test) and a BISR (built-in self repair) are individually performed in response to an additional command signal.
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