Efficient integrated circuit layout scheme to implement a scalable switching network used in interconnection fabric
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United States of America Patent
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Sep 9, 2008
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app pub date -
Jan 20, 2006
filing date -
Jan 20, 2006
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Abstract
Efficient layout schemes to implement switching networks of an interconnection fabric in an integrated circuit to connect two sets of conductors through rows of switches with prescribed number of tracks over the switching area are described. The layout schemes can be used repeatedly for multiple-stage switching network and/or hierarchically arranged switching networks.
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