Architecture and related methods for efficiently performing complex arithmetic
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United States of America Patent
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Sep 9, 2008
Grant Date -
Nov 14, 2002
app pub date -
Mar 31, 2001
filing date -
Mar 31, 2001
priority date (Note) -
Expired
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Abstract
A method is presented comprising analyzing two or more input terms on a per-bit basis within each level of bit-significance. Maximally segmenting each of the levels of bit-significance into one or more one-, two-, and/or three-bit groups, and designing a hyperpipelined hybrid Wallace tree adder utilizing one or more full-adders, half-adders, and associated register based, at least in part, on the maximal segmentation of the input terms.
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