Switch for bus optimization
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United States of America Patent
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Sep 16, 2008
Grant Date -
Jul 14, 2005
app pub date -
Jan 7, 2005
filing date -
Jan 8, 2004
priority date (Note) -
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Abstract
There is disclosed a bus optimization technique. Pursuant to the bus optimization technique, the output buffer and output logic are removed from port units of a switch and are included with a control matrix in the switch. Data units received in a first port unit of a plurality of port units are provided to a control matrix. The control matrix evaluates when to send the data unit to a second port unit. No output decisions are made in the second port unit.
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