Multiple select gates with non-volatile memory cells
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United States of America Patent
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Oct 7, 2008
Grant Date -
Nov 1, 2007
app pub date -
Apr 26, 2006
filing date -
Apr 26, 2006
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Abstract
Multiple select gates in association with non-volatile memory cells are described. Various embodiments include multiple select gate structure, process, and operation and their applicability for memory devices, modules, and systems. In one embodiment a memory array is described. The memory array includes a number of select gates coupled in series to a number of non-volatile memory cells. A first select gate includes a control gate and a floating gate electrically connected together and a second select gate includes a control gate and a floating gate which are electrically separated by a dielectric layer.
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