NAND memory array incorporating capacitance boosting of channel regions in unselected memory cells and method for operation of same
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United States of America Patent
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Oct 7, 2008
Grant Date -
Oct 18, 2007
app pub date -
Jun 18, 2007
filing date -
Dec 31, 2002
priority date (Note) -
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Abstract
An exemplary NAND string memory array provides for capacitive boosting of a half-selected memory cell channel to reduce program disturb effects of the half selected cell. To reduce the effect of leakage current degradation of the boosted level, multiple programming pulses of a shorter duration are employed to limit the time period during which such leakage currents may degrade the voltage within the unselected NAND strings. In addition, multiple series select devices at one or both ends of each NAND string further ensure reduced leakage through such select devices, for both unselected and selected NAND strings. In certain exemplary embodiments, a memory array includes series-connected NAND strings of memory cell transistors having a charge storage dielectric, and includes more than one plane of memory cells formed above a substrate.
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