Method and apparatus for memory self testing

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 7434119
APP PUB NO 20060200713A1
SERIAL NO

11072626

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Abstract

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A memory self-test system is provided comprising a self-test controller operable in self-test mode to generate a sequence of generated memory addresses for performing memory access operations associated with the memory test algorithm having an associated memory cell physical access pattern. A programmable re-mapper is operable to re-map the sequence of generated memory addresses derived from the self-test instruction to a sequence of re-mapped memory addresses. The programmable re-mapper performs this re-mapping in response to programmable mapping selection data. The re-mapping of the generated memory addresses to re-mapped memory addresses ensures that the memory cell accesses performed during execution of the memory self-test are consistent with the associated memory cell physical access pattern regardless of the particular implementation of the memory array.

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Patent Owner(s)

Patent OwnerAddress
ARM LIMITEDCAMBRIDGE

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Frederick, Frank David Austin, TX 9 38
Slobodnik, Richard Austin, TX 10 495

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