Lithographically optimized placement tool
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United States of America Patent
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Oct 7, 2008
Grant Date -
N/A
app pub date -
Mar 9, 2006
filing date -
Mar 9, 2006
priority date (Note) -
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Abstract
A system and a method are disclosed for integrating the results of lithographic simulation into the physical synthesis process. The effects of lithographic variation are considered when selecting a cell from among a group of cells having equivalent function. Circuit design elements are placed and routed with consideration of the effects of lithographic variation on robustness, timing performance, and leakage current. Cells may be simulated under a variety of conditions and environments and the simulation results stored in a library for efficient lithographically optimized placements.
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