NAND flash memory with boosting
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United States of America Patent
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Oct 14, 2008
Grant Date -
Nov 8, 2007
app pub date -
May 5, 2006
filing date -
May 5, 2006
priority date (Note) -
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Abstract
A floating gate memory array includes row control circuits that provide a programming voltage to a selected word line and provide a stair-like pattern of boosting voltages to unselected word lines. Boosting voltages descend with increased distance from the selected word line. Boosting voltages are increased in small increments up to their final values.
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