System and method for controlling application of an error correction code (ECC) algorithm in a memory subsystem
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United States of America Patent
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Oct 14, 2008
Grant Date -
Dec 29, 2005
app pub date -
Jun 29, 2004
filing date -
Jun 29, 2004
priority date (Note) -
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Abstract
A method for controlling application of an erasure mode of an error correction code (ECC) algorithm in a memory subsystem includes detecting errors in cache lines retrieved from the memory subsystem using the ECC algorithm. The method also analyzes the errors to detect a repeated bit pattern of data corruption within the cache lines, correlates the detected repeated bit pattern of data corruption to one of a plurality of domains of the memory subsystem, and applies the ECC algorithm to erase bits associated with the detected repeated bit pattern from cache lines retrieved from the correlated domain of the memory subsystem.
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