Method of memory and run-time efficient hierarchical timing analysis in programmable logic devices
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United States of America Patent
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Oct 14, 2008
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N/A
app pub date -
Apr 5, 2005
filing date -
Mar 3, 2004
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Abstract
A method of performing timing analysis on a circuit design for an integrated circuit (IC) can include selecting a physical portion of the IC that includes at least one instance of a logic hierarchy and generating a local timing constraint specific to the physical portion. The method also can include creating a software representation of the physical portion of the IC. The software representation can specify the local timing constraint and a shell netlist for the physical portion. The method further can include performing a timing analysis upon, at least part of, the circuit design using the software representation.
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