Method and apparatus for performing synthesis to improve density on field programmable gate arrays
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United States of America Patent
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Oct 21, 2008
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Jan 7, 2005
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Jan 7, 2005
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Abstract
A method for designing a system on a programmable logic device (PLD) includes implementing a first network of logic elements (LEs) and a second network of LEs with a combined network of LEs that performs a same functionality but utilizes a fewer number of LEs.
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