Semiconductor memory device with a voltage generating circuit which generates a plurality of voltages using a small number of items of data
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United States of America Patent
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Oct 28, 2008
Grant Date -
Mar 22, 2007
app pub date -
Sep 14, 2006
filing date -
Sep 22, 2005
priority date (Note) -
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Abstract
In a memory cell array, a plurality of memory cells connected to word lines and bit lines are arranged in a matrix. A storage section stores an initial value of a write voltage corresponding to a first write operation and a correction value for correcting the write voltage. A voltage generating circuit generates a word line write voltage in a first write operation or a second write operation on the basis of the initial value and correction value of the write voltage stored in the storage section.
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