Semiconductor die package with internal bypass capacitors
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United States of America Patent
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Nov 4, 2008
Grant Date -
Dec 22, 2005
app pub date -
Jul 8, 2005
filing date -
Jun 17, 2004
priority date (Note) -
Expired
status (Latency Note)
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Abstract
One embodiment of the present invention provides an apparatus that reduces voltage noise for an integrated circuit (IC) device. This apparatus includes a package which is configured to be sandwiched between the IC device and a circuit board. This package has a bottom surface, which is configured to receive electrical connections for power, ground and other signals from the circuit board, and a top surface, which is configured to provide electrical connections for power, ground and the other signals to the IC device. A plurality of bypass capacitors are integrated into the package and are coupled between the power and ground connections for the IC device, so that the plurality of bypass capacitors reduce voltage noise between the power and ground connections for the IC device.
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