Method of fabricating a high-layer-count backplane
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United States of America Patent
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Nov 11, 2008
Grant Date -
Feb 22, 2007
app pub date -
Oct 2, 2006
filing date -
Feb 5, 2002
priority date (Note) -
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Abstract
The disclosed board fabrication techniques and design features enable the construction of a reliable, high-layer-count, and economical backplane for routers and the like that require a large number of signaling paths across the backplane at speeds of 2.5 Gbps or greater, as well as distribution of significant amounts of power to router components. The disclosed techniques and features allow relatively thick (e.g., three- or four-ounce copper) power distribution planes to be combined with large numbers of high-speed signaling layers in a common backplane. Using traditional techniques, such a construction would not be possible because of the number of layers required and the thickness of the power distribution layers. The disclosed embodiments use novel layer arrangements, material selection, processing techniques, and panel features to produce the desired high-speed layers and low- noise high-power distribution layers in a single mechanically stable board.
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- 15 United States
- 10 France
- 8 Japan
- 7 China
- 5 Korea
- 2 Other
Patent Owner(s)
| Patent Owner | Address | |
|---|---|---|
| DELL MARKETING CORPORATION | ONE DELL WAY ROUND ROCK TX 78682 |
International Classification(s)
Inventor(s)
| Inventor Name | Address | # of filed Patents | Total Citations |
|---|---|---|---|
| Goergen, Joel R | San Jose, CA | 43 | 735 |
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| Fee | Large entity fee | small entity fee | micro entity fee |
|---|---|---|---|
| Surcharge after expiration - Late payment is unavoidable | $700.00 | $350.00 | $175.00 |
| Surcharge after expiration - Late payment is unintentional | $1,640.00 | $820.00 | $410.00 |
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