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Abstract

The present invention relates to the control of an array of processing elements in a parallel processor using row and column select lines. For each column in the array, a column select line connects to all of the processing elements in the column. For each row in the array, a row select line connecting to all of the processing elements in the row. A processing element in the array may be selected by activation of its row and column select lines. The processing elements are connected to adjacent processing elements by respective segments of a row bus for each row and by respective segments of a column bus for each column. Each row of the array includes a respective column edge register coupled to a processing element at one end of the respective row and to a processing element at the other end of the respective row. Similarly, each column of the array includes a respective row edge register coupled to a processing element at one end of the respective row and to a processing element at the other end of the respective row. The column edge registers allow digital signals to be coupled between the processing elements at the ends of the respective row, and the row edge registers allow digital signals to be coupled between the processing elements at the ends of the respective column.

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First Claim