ASIC clock floor planning method and structure
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Nov 18, 2008
Grant Date -
Feb 9, 2006
app pub date -
Dec 17, 2002
filing date -
Dec 17, 2002
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A method of designing a clock tree in an integrated circuit combines steps of making a list of all clock sinks; positioning a temporary reference insertion point (TIP); grouping the sinks together with structured clock buffers (SCBs) in a set of levels; and moving the SCBs to improve symmetry of the tree. The SCBs may be of several sizes and may be positioned horizontally or vertically and moved within limits to permit the program to calculate a complete tree.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully