Erase voltage manipulation in non-volatile memory for controlled shifts in threshold voltage
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United States of America Patent
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Nov 25, 2008
Grant Date -
Jan 17, 2008
app pub date -
Jul 5, 2007
filing date -
Mar 31, 2005
priority date (Note) -
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Abstract
The erase voltage applied to a set of non-volatile storage elements being erased is structured to provide controlled shifts in the threshold voltage of the storage elements. The erase voltage is applied as a series of voltage pulses, when necessary, to shift the threshold voltage of to-be-erased memory cells below a verify level indicative of an erased condition. To avoid over-erasing the memory cells, the second erase voltage pulse is decreased, or not increased, in magnitude when compared to the previously applied voltage pulse. By decreasing or not increasing the size of the erase voltage, the amount of charge transferred from the cells by the second pulse is controlled to more accurately position an erased threshold voltage distribution for the cells near the verify level. Subsequent erase voltage pulses are increased in magnitude to provide further erasing when needed.
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