Method and apparatus for providing packed shift operations in a processor
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United States of America Patent
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-
Dec 2, 2008
Grant Date -
Oct 11, 2007
app pub date -
Jun 6, 2007
filing date -
Dec 1, 1994
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A method and apparatus for providing, in a processor, a shift operation on a packed data element having multiple values. One embodiment of a central processing unit (CPU) includes instruction fetch logic to fetch a single-instruction-multiple-data (SIMD) shift instruction. A register stores a multiple data elements to be operated upon by the SIMD shift instruction. A barrel shifter concurrently shifts the data elements in a bit-wise manner by a variable number of bit positions in response to the SIMD shift instruction.
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