System and method for using a learning sequence to establish communications on a high-speed nonsynchronous interface in the absence of clock forwarding
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United States of America Patent
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Dec 2, 2008
Grant Date -
Sep 14, 2006
app pub date -
May 11, 2006
filing date -
Oct 27, 2003
priority date (Note) -
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status (Latency Note)
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Abstract
A memory system includes a memory hub controller that sends write data to a plurality of memory modules through a downstream data bus and receives read data from the memory modules through an upstream data bus. The memory hub controller includes a receiver coupled to the upstream data bus and a transmitter coupled to the downstream data bus. Similarly, each of the memory modules includes a receiver coupled to the downstream data bus and a transmitter coupled to the upstream data bus. Each receiver includes a receive clock generator that is synchronized by coupling a known pattern of data to the receiver. The receiver determines which phase of the receive clock best captures the known pattern and uses that receive clock phase during normal operation.
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