Partial erase verify

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United States of America Patent

PATENT NO 7468926
APP PUB NO 20060158940A1
SERIAL NO

11335321

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Abstract

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A method for erasing memory cells in a memory array, the method including applying an erase pulse to bits of a cell ensemble of a memory cell array, and performing an erase verification operation only on a subgroup of the cell ensemble being erased to check if the memory cells threshold voltage (Vt) has been lowered to an erase verify (EV) voltage level.

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Patent Owner(s)

  • SAIFUN SEMICONDUCTORS LTD.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Eisen, Shai Tel Aviv, IL 7 585
Shappir, Assaf Kiryat Ono, IL 43 383

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