Wafer flatness evaluation method, wafer flatness evaluation apparatus carrying out the evaluation method, wafer manufacturing method using the evaluation method, wafer quality assurance method using the evaluation method, semiconductor device manufacturing method using the evaluation method and semiconductor device manufacturing method using a wafer evaluated by the evaluation method

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United States of America Patent

PATENT NO 7474386
APP PUB NO 20070177127A1
SERIAL NO

11710552

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Abstract

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There is disclosed a wafer flatness evaluation method includes measuring front and rear surface shapes of a wafer. The wafer front surface measured is divided into sites. Then, a flatness calculating method is selected according to a position of the site to be evaluated and flatness in the wafer surface is acquired.

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Patent Owner(s)

Patent OwnerAddress
KIOXIA CORPORATIONTOKYO

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Fujisawa, Tadahito Tokyo , JP 47 884
Hagiwara, Tsuneyuki Tokyo , JP 47 1353
Ichikawa, Masashi Nishishirakawa-gun , JP 15 177
Inoue, Soichi Yokohama , JP 131 2548
Kobayashi, Makoto Nishishirakawa-gun , JP 647 7424
Kodama, Kenichi Mito , JP 57 732

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