Selective formation of metal layers in an integrated circuit

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 7476618
APP PUB NO 20060121733A1
SERIAL NO

11254071

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Abstract

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A method for enhancing the reliability of copper interconnects and/or contacts, such as the bottom of vias exposing top surfaces of buried copper, or at the top of copper lines just after CMP. The method comprises contacting the exposed copper surface with a vapor phase compound of a noble metal and selectively forming a layer of the noble metal on the exposed copper surface, either by a copper replacement reaction or selective deposition (e.g., ALD or CVD) of the noble metal.

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Patent Owner(s)

Patent OwnerAddress
ASM JAPAN K K23-1 6-CHOME NAGAYAMA TAMA-SHI TOKYO 206-0025

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Huotari, Hannu A Espoo , FI 3 232
Kilpela, Olli V Helsinki , FI 2 229
Koh, Wonyong Hachioji , JP 21 1513
Leinikka, Miika Vantaa , FI 6 715
Tuominen, Marko Helsinki , FI 102 10592

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