Methods and apparatus for packaging integrated circuit devices
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United States of America Patent
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Jan 20, 2009
Grant Date -
Jan 24, 2008
app pub date -
Aug 21, 2007
filing date -
Jul 3, 2003
priority date (Note) -
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Abstract
An integrally packaged integrated circuit device including an integrated circuit die including a crystalline substrate having first and second generally planar surfaces and edge surfaces and semiconductor circuitry formed over the first generally planar surface, at least one chip scale packaging layer formed over the semiconductor circuitry and the first generally planar surface, an insulation layer formed over the second generally planar surface and the edge surfaces and at least one electrical conductor formed directly on the insulation layer overlying the second generally planar surface, the at least one electrical conductor being connected to the circuitry by at least one pad formed directly on the first generally planar surface.
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