Memory component with multiple delayed timing signals
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United States of America Patent
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Jan 20, 2009
Issued Date -
N/A
app pub date -
May 8, 2007
filing date -
Sep 15, 2004
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Abstract
A memory component having multiple delayed timing signals. Control information specifying a write operation and write data corresponding to the write operation are each received via a separate external signal path. A timing signal is received indicating that the write data is valid write data. Signals corresponding to multiple delayed versions of the timing signal are output for use in determining a propagation delay time between the control information and the write data.
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