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Abstract

In one aspect of the invention, a digital watermark detector comprises a memory buffer for managing an incoming stream of data. The detector includes logic for transferring overlapping data blocks from the memory buffer to a frequency domain transform processor, such as an FFT processor. The frequency domain transform processor including logic to re-use frequency domain transform operation results for overlapping portions of the data blocks. In another aspect of the invention, a digital watermark detector comprises a memory buffer for a block of data, and pipelined watermark processor segments. The segments each perform different watermark detector operations in series. These segments concurrently operate on different data segments of the block of data in a processing pipeline. One embodiment employs pipelined processors for setting up data for subsequent detecting stages, such as pipelined data conversion, re-sampling, pre-filtering and frequency domain transforms. Alternative embodiments pipeline data transformations, correlation operations (e.g., matched filter operations) etc. Data flows through the processing pipeline until it reaches a critical point. At stages before the critical point, data may be dropped as not likely to include digital watermark data. This pruning of data helps reduce un-needed processing and/or false positives of watermark detection.

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First Claim