Method and apparatus to increase the usable memory capacity of a logic simulation hardware emulator/accelerator
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United States of America Patent
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Jan 20, 2009
Grant Date -
Nov 17, 2005
app pub date -
May 13, 2004
filing date -
May 13, 2004
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A method, apparatus and program product are provided for increasing the usable memory capacity of a logic simulation hardware emulator. The present invention performs an additional logic synthesis operation during model build to transform an original logical array within a logic model into a transformed logical array, such that a row within the transformed logical array includes a plurality of merged logical array rows from the original logical array. The invention further modifies read and write port logic surrounding the transformed logical array during the logic synthesis operation to support read and write accesses during model emulation run time.
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